Available at: https://digitalcommons.calpoly.edu/theses/3336
Date of Award
6-2026
Degree Name
MS in Electrical Engineering
Department/Program
Electrical Engineering
College
College of Engineering
Advisor
Maria Pantoja
Advisor Department
Electrical Engineering
Advisor College
College of Engineering
Abstract
Modern computing has relied on multicore processors for high performance for nearly two decades, yet undergraduate computer engineering curricula often provide limited exposure to parallel hardware architectures and their design challenges. This thesis presents the design of CPE 433, a course that extends the pipelined and cached OTTER CPU developed in CPE 233 and CPE 333 into a multicore processor capable of running parallel workloads. The thesis documents the architectural changes required to adapt the verified single-core design into a multicore system, including MMIO-based interrupt support, a shared cache hierarchy with cache-coherence mechanisms, and clock-gated modules. It further presents a working multicore CPU implementation, analyzes the principal challenges encountered during the transition from a single-core to a multicore design, and derives a 10-week project structure together with a resource guide for instructors and students undertaking similar projects.
Notes
My advisor is in the computer engineering department, which is not apart of the drop down menu. I selected electrical engineering as that is the department I am getting my degree from.