Available at: https://digitalcommons.calpoly.edu/theses/3259
Date of Award
4-2026
Degree Name
MS in Electrical Engineering
Department/Program
Electrical Engineering
College
College of Engineering
Advisor
Taufik
Advisor Department
Electrical Engineering
Advisor College
College of Engineering
Abstract
The increasing energy demand in data centers driven by artificial intelligence has intensified the need for highly efficient voltage regulator modules (VRMs) to reduce electricity consumption and improve thermal management. The High Step-Down (HSD) converter studied in this thesis offers a novel high‑efficiency DC–DC step‑down topology tailored to the large voltage conversion ratios and high output currents characteristic of data center VRMs. Theoretical power loss equations are derived for each loss mechanism in both the HSD converter and the synchronous buck converter, enabling direct comparison between the two topologies. A 40 W HSD and buck hardware prototype operating with 12 V input voltage and 1 V output volage is used to define the parameters of the loss model and an LTspice simulation, allowing comparison between theoretical predictions, simulation results, and experimental measurements for both topologies. Results show that the HSD converter achieves higher theoretical efficiency than the buck converter for output currents below 30 A, whereas the buck converter becomes more efficient at currents above this threshold. At the 40 A maximum‑load operating condition, the dominant theoretical loss mechanisms in the HSD converter are low‑side MOSFET conduction (31.05%), dead‑time conduction (22.79%), and high‑side and middle‑switch MOSFET conduction (8.62% each). In comparison, the buck converter’s dominant loss mechanisms at 40 A are low‑side MOSFET conduction (28.96% of total loss), followed by dead‑time conduction (20.50%) and high‑side MOSFET conduction (18.40%).