A Study on Quantization and Hardware Cost Tradeoffs in a 5G NR LDPC Decoder on FPGA

Author

• Giancarlo AcostaFollow

Available at: https://digitalcommons.calpoly.edu/theses/3335

Date of Award

6-2026

Degree Name

MS in Electrical Engineering

Department/Program

Electrical Engineering

College

College of Engineering

Advisor

Andrew Danowitz

Advisor Department

Electrical Engineering

Advisor College

College of Engineering

Abstract

The fixed-point implementation of a 5G New Radio LDPC decoder forces a tradeoff between precision and hardware cost, governed by the variable node word length W_L, the check node message width W_R, and the normalized min-sum correction factor α. This thesis characterizes how these three parameters affect both error correction performance and FPGA resource utilization for an LDPC decoder on an established LDPC decoder architecture. A bit-accurate MATLAB core model records bit error rate (BER) and frame error rate (FER) while a verified HDL Coder model generates synthesizable VHDL for Vivado synthesis, and both are swept over W_L, W_R, and α at lifting sizes Z = 64 and Z = 384. The results show that α is effectively free in hardware cost, while W_L costs far more per bit than W_R, because W_L largely dominates the decoder’s critical path and memory units. For configurations that reach the 5 × 10^-5 BER target, the SNR required to reach the target varies by approximately 0.05 dB, so hardware cost dominates parameter selection and points to a smallest passing operating point of W_L = 6 and W_R = 5.