Available at: https://digitalcommons.calpoly.edu/theses/3314
Date of Award
6-2026
Degree Name
MS in Electrical Engineering
Department/Program
Electrical Engineering
College
College of Engineering
Advisor
Payam Nayeri
Advisor Department
Electrical Engineering
Advisor College
College of Engineering
Abstract
In the world of small satellites, there is growing interest in higher-data-rate systems and the technologies that enable them. Due to limitations in the extremely reliable and proven Ultra-High Frequency (UHF) systems, the current CubeSats developed by the Cal Poly CubeSat Laboratory operate at 9600 Baud. However, the low Baud rate is rooted in decades of proven flights and is very resistant to many forms of signal degradation. While a slow but simple system was critical to past successes, future satellite payloads may require higher data rates to drastically reduce the number of passes needed to transfer large amounts of data. To address this need, this work conceptualizes a high-data-rate CubeSat system with an S-band uplink of at least 1 Mbps. As part of the CubeSat’s receive portion, several transistor-level discrete low-noise amplifiers are designed, simulated, and tested. Specifically, two topologies are investigated: single-stage and cascode configurations. Single-stage amplifiers offer medium gain and low noise figure in return for their simplicity, while cascode designs have high gain and low noise but require more components and greater complexity. Both amplifiers are designed using OshPark's FR4 substrate and surface-mount components. Laboratory testing showed the single-stage PCB had a gain of 14 dB and a noise figure (NF) of 1.36 dB. While the cascode achieved good simulation results, the PCB design ultimately could not provide gain at the desired frequencies. With the designs fabricated and tested, an uplink system test was performed where BPSK-modulated data was passed through a designed amplifier without any bit errors.