Available at: https://digitalcommons.calpoly.edu/theses/3234
Date of Award
3-2026
Degree Name
MS in Computer Science
Department/Program
Computer Science
College
College of Engineering
Advisor
Stephen Beard
Advisor Department
Computer Science
Advisor College
College of Engineering
Abstract
Hardware verification engineers apply formal methods to prove that a digital device always behaves according to its specification. This differs from traditional functional verification, in which engineers establish correctness by repeatedly sending test inputs to the device and comparing the outputs against a reference model. With the growing complexity of integrated circuits, the demand for digital verification engineers with formal methods experience has continued to increase. However, California Polytechnic State University: San Luis Obispo's current curriculum lacks dedicated material to prepare students for these roles.
This thesis seeks to address the lack of formal methods material through two efforts. First, formal and functional verification techniques are applied to two educational RISC-V processors. These case studies demonstrate that applying open-source formal methods tooling is achievable for undergraduates and provides greater functional coverage than simple simulation testing. Building from these cases, this thesis contributes a pair of formal verification workshops that could be integrated into future courses. A preliminary run of the coursework validated its effectiveness in conveying formal verification concepts and helped address remaining flaws in the material.
Included in
Computer and Systems Architecture Commons, Curriculum and Instruction Commons, Discrete Mathematics and Combinatorics Commons, Educational Assessment, Evaluation, and Research Commons, Logic and Foundations Commons, Theory and Algorithms Commons, VLSI and Circuits, Embedded and Hardware Systems Commons