Date of Award

6-2025

Degree Name

MS in Electrical Engineering

Department/Program

Electrical Engineering

College

College of Engineering

Advisor

Stephen Beard

Advisor Department

Computer Science

Advisor College

College of Engineering

Abstract

FPGAs have long been used for prototyping and verifying high-speed digital designs in industry and in academic research. As ASIC designs have grown in complexity and size, prototyping those designs on FPGAs has required multiple FPGAs that sometimes span multiple servers. Western Digital donated multiple FPGA-based systems to Cal Poly in 2023. These servers contain multiple high-end AMD FPGAs that are ideal for prototyping large high-speed digital designs, however the full documentation on how to use the servers and how the servers work was not provided. The servers did not come with any information on how to program the FPGAs, how to use the software that was preloaded onto the systems, or how to interact with many of the hardware interfaces. Multiple faculty members have projects that could benefit from prototyping on large FPGA systems, however none of the faculty at Cal Poly know how to program the FPGAs, or utilize the high-speed communication links between the FPGAs. This thesis lays out the debugging and reverse engineering steps that were taken to understand and bring up these servers. It specifically details how to program the FPGAs, how to use the debug interfaces, how to program the onboard clock generators, and how to use the high-speed interconnects between the FPGAs and between the systems. It also details several example designs for verifying and profiling these interconnects and characterizes these interconnects in terms of throughput and latency. Finally this thesis generalizes the takeaways from reverse engineering these systems to steps that can be taken when reverse engineering complex hardware/software systems.

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