Available at: https://digitalcommons.calpoly.edu/theses/2980
Date of Award
3-2025
Degree Name
MS in Electrical Engineering
Department/Program
Electrical Engineering
College
College of Engineering
Advisor
John Oliver
Advisor Department
Electrical Engineering
Advisor College
College of Engineering
Abstract
As machine learning models such as neural networks are investigated for their applications across many fields, the demand for models that can be implemented on an embedded device grows. Field Programmable Gate Arrays (FPGAs) have become an attractive option for implementing these models in hardware. This thesis considers the viability of FPGA implementations for machine learning on low-resourced embedded systems. The hls4ml project is a promising prospect for machine learning on FPGA devices. To test hls4ml, we used a model trained on the MNIST digits dataset, which was then synthesized for the PYNQ-Z2 device. We fine tuned the performance by changing the reuse factor and quantization used by hls4ml. These designs were tested on throughput, latency, power usage, and utilization of resources on the device. We found significant changes in the accuracy and classification speed using relatively minor changes in the precision of the overall model. Other frameworks and design strategies found in literature were also compared.
