Available at: https://digitalcommons.calpoly.edu/theses/2925
Date of Award
6-2023
Degree Name
MS in Electrical Engineering
Department/Program
Electrical Engineering
College
College of Engineering
Advisor
Andrew Danowitz
Advisor Department
Electrical Engineering
Advisor College
College of Engineering
Abstract
To improve the accuracy and resolution of the measurements, radar systems employ increasingly complex, resource-intensive signal processing, larger bandwidths, and higher carrier frequencies. However, implementing these improvements requires more expensive, complex electronics that are larger and use more power. Using RFSoC (Radio Frequency System on Chips) in radars can address these challenges. By combining processors, an FPGA (Field Programmable Gate Array), and RF data converters into a single integrated circuit, RFSoCs allow for radar electronics that are physically smaller, use less power, and are simpler to design. As using RFSoCs to perform RF data conversion for radars has been already explored, this work focuses on performing radar processing for a marine radar with an RFSoC. Performance specifications for a marine radar are defined based on the specifications for other modern marine radars, a suitable radar waveform is designed based on the derived performance specifications, and a processing chain to compute the range-doppler map is implemented based on the radar specifications and waveform. The processing chain, created as a block design in the Vivado Design Suite, consists of matched filtering and doppler processing. The processing chain is simulated in Vivado and implemented on the FPGA of a Xilinx ZCU216 RFSoC Evaluation Board. To verify the operation of the processing chain, the range-doppler maps generated by simulation and from running the design on the ZCU216 board are compared with range-doppler maps generated by a processing model implemented in MATLAB. The range-doppler map processing chain performs correctly as the outputs from simulation and the ZCU216 show close agreement with the MATLAB results with average percent differences on the order of 10-4 % to 10-5 % and average differences on the order of 10-7. The processing chain generates the range-doppler map quickly: the final range-doppler value is output 1.75 milliseconds after the final sample of a CPI (Coherent Processing Interval) of radar data (the total CPI duration is 10.49 milliseconds) is input. The FPGA resource usage of the processing chain is 85% of the BRAM, 0% of the URAM, 0.87% of the DSP slices, and approximately 1% of the configurable logic blocks. The low resource usage of the processing chain allows for possibilities of future expansion of the processing chain to include radar processing techniques such as digital beamforming or threshold estimation.