Date of Award


Degree Name

MS in Electrical Engineering


Electrical Engineering


College of Engineering


Joseph Callenes-Sloan, Andrew Robert Danowitz

Advisor Department

Electrical Engineering

Advisor College

College of Engineering


Graphics Processing Units (GPUs) are commonly used to accelerate massively parallel workloads across a wide range of applications from machine learning to cryptocurrency mining. The original application for GPUs, however, was to accelerate graphics rendering which remains popular today through video gaming and video rendering. While GPUs began as fixed function hardware with minimal programmability, modern GPUs have adopted a design with many programmable cores and supporting fixed function hardware for rasterization, texture sampling, and render output tasks. This balance enables GPUs to be used for general purpose computing and still remain adept at graphics rendering. Previous work at the Georgia Institute of Technology has been done to implement a general purpose GPU (GPGPU) in the open source RISC-V ISA. The implementation features many programmable cores and texture sampling support. However, creating a truly modern GPU based on the RISC-V ISA requires the addition of fixed function hardware units for rasterization and render output tasks in order to meet the demands of current graphics APIs such as OpenGL or Vulkan. This thesis discusses the work done by students at the Georgia Institute of Technology and California Polytechnic State University SLO to accelerate graphics rendering on RISC-V GPUs including the specific contributions made to implement and connect fixed function graphics hardware for the render output unit (ROP) to the programmable cores in a RISC-V GPU. This thesis also explores the performance and area cost of different hardware configurations within the implemented GPU.