Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz

Author

Run Bin Yu, California Polytechnic State University, San Luis ObispoFollow

DOI: https://doi.org/10.15368/theses.2016.164
Available at: https://digitalcommons.calpoly.edu/theses/1685

Date of Award

12-2016

Degree Name

MS in Electrical Engineering

Department/Program

Electrical Engineering

Advisor

Tina H. Smilkstein

Abstract

The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the clock edge, could undermine the overall performance or even cause failures on the system. Deterministic jitter could be reduced during the designing process however random jitter during operation is somehow less-controllable and unavoidable. Being able to remove jitter on the clock would therefore play a vital role in system performance improvement.

This thesis implements a 1GHz fully feedforward jitter reduction circuit (JRC) which can be used as an on-chip IP core at clock tree terminals to provide a low jitter clock signal to a local clock network or be used at the clock insertion point to reduce jitter from an off chip signal. It can also be stand-alone and used on PCB designs to reduce jitter on the high-frequency clock signal used on the board. This jitter attenuation circuit is implemented using IBM CMHV7SF 180nm MOSFET process, demonstrates a jitter reduction of at least 8dB at 1GHz with 33ps rms Gaussian random jitter (for a 200ps peak-to-peak randomly changing rising edge input signal).