Available at: https://digitalcommons.calpoly.edu/theses/35
Date of Award
MS in Electrical Engineering
The power requirements for microprocessors have been increasing per Moore's Law. According to International Technology Roadmap (ITRS), Voltage Regulator Module (VRM) for microprocessors will be about 200 W at 1 V output in 2010. With the VRM’s topology of synchronous buck, serious technical challenges such as small duty cycle, high switching frequencies, and higher current demands, contribute to decreased power density and increased cost.
This thesis proposes a Continuous Input Current Multiphase Interleaved Buck topology to solve the technical challenges of powering future microprocessors. This new topology is aimed to improve past topologies by providing continuous input current and improved efficiency. An open loop system of the proposed new topology is simulated using OrCAD PSpice to evaluate the performance criteria of the VRM. A hardware prototype of a four-phase Continuous Input Current Multiphase Interleaved Buck Converter is constructed and tested to assess the targeted improvements.