Available at: https://digitalcommons.calpoly.edu/theses/102
Date of Award
MS in Electrical Engineering
As the transistor count per chip in computer microprocessors surpasses one billion, the semiconductor industry has become more and more concerned with meeting processor’s power requirements. This poses a design challenge for the power supply module, especially when the processor operates at low voltage range. For example, the electrical requirement for the newest Intel microprocessors has exceeded 100A with an input voltage of approximately 1V. To overcome this problem, multiphase DC-to-DC converters encased in a voltage regulator module (VRM) have become the standard means of supplying power to computer microprocessor.
This study proposes a new topology for the multiphase DC-to-DC converter for powering microprocessors. The new topology accepts 12 V input, and outputs a steady state voltage of 1 V with a maximum output current of 40 A. The proposed topology aims to improve the input and output characteristics of the basic multiphase “buck” converter, along with an improved efficiency, line regulation, and load regulation.
To explore the feasibility of such a topology, open-loop computer simulation and closed-loop hardware tests were performed. On open-loop simulation, OrCad pspice was used to verify design calculations and evaluate its performance. Then the closed-loop hardware prototype was tested to compare the circuit performance with those values obtained from simulation.
The result shows the proposed topology improvement of efficiency, board size, output ripple, and regulations.