College - Author 1
College of Engineering
Department - Author 1
Electrical Engineering Department
Degree Name - Author 1
BS in Electrical Engineering
College - Author 2
College of Engineering
Department - Author 2
Electrical Engineering Department
Degree - Author 2
BS in Electrical Engineering
College - Author 3
College of Engineering
Department - Author 3
Electrical Engineering Department
Degree - Author 3
BS in Electrical Engineering
Date
6-2026
Primary Advisor
Anu Aggarwal, College of Engineering, Electrical Engineering Department
Abstract/Summary
This project presents the design and implementation of a 2 layer test-bench printed circuit board (PCB) for evaluating the functionality of a custom 40-pin VLSI integrated circuit. The objective is to create a reliable and portable platform capable of supplying configurable bias voltages, generating variable input signals, and monitoring both analog and digital outputs. The board integrates adjustable bias networks using potentiometers, digital and analog buffering stages, and optional battery supply operation. The VLSI device under test is mounted in dual-in-line (DIP) sockets to enable rapid replacement and repeated characterization. Dedicated test points are incorporated throughout the PCB to facilitate measurement with standard laboratory instrumentation. The development process includes circuit selection, component specification, schematic creation, and PCB layout using ExpressPCB design software, followed by board fabrication, assembly, and experimental validation using an oscilloscope, multimeter, power supply, and function generator. The resulting system provides a structured and flexible test platform suitable for comprehensive characterization of the VLSI chip's electrical performance.
URL: https://digitalcommons.calpoly.edu/eesp/719