College - Author 1
College of Engineering
Department - Author 1
Electrical Engineering Department
Degree Name - Author 1
BS in Electrical Engineering
College - Author 2
College of Engineering
Department - Author 2
Electrical Engineering Department
Degree - Author 2
BS in Electrical Engineering
College - Author 3
College of Engineering
Department - Author 3
Electrical Engineering Department
Degree - Author 3
BS in Electrical Engineering
College - Author 4
College of Engineering
Department - Author 4
Electrical Engineering Department
Degree - Author 4
BS in Electrical Engineering
Date
6-2026
Primary Advisor
Nishith Chakraborty, College of Engineering, Electrical Engineering Department
Abstract/Summary
A spike encoder forms the interface between sampled data, such as image data or a sensor signal, and a spiking neural network by converting numerical input samples into discrete spike events. Unlike conventional artificial neural networks, spiking neural networks use spare, even-driven computation instead of continuous-valued activations. This makes them attractive for low-power embedded systems, biomedical electronics, and other edge applications where energy consumption, physical area, and thermal limits are important design constraints.
This project develops a modular spike encoder architecture for spiking neural networks with selectable support for temporal, rate, multi-spike, and delta encoding. Prior work has shown that hardware spike encoders can be made runtime reconfigurable, allowing the same system to evaluate multiple encoding schemes without rebuilding the hardware. The target application is electrocardiogram signal processing for heart arrhythmia detection, where sampled ECG data must be converted into spike trains that preserve timing and slope information for a downstream trained neural network. The digital encoder is parameterized to support input resolution up to 12 bits, including compatibility with 11-bit MIT-BIH Arrhythmia Dataset samples. For the custom mixed-signal VLSI demonstration, a 4-bit SAR ADC using a capacitive DAC was implemented as a proof-of-concept due to project time, process, and layout constraints.
The final system includes a runtime-selectable spike encoder, FPGA verification using UART-streamed ECG data, and ASIC synthesis of the encoder logic. FPGA synthesis showed that the full selectable encoder used 204 LUTs and 112 flip-flops at 100 Mhz, with power near 0.061 W. ASIC synthesis showed that the full encoder required 12,829.8 square micrometers, 970 standard cells, 162 sequential cells, and 0.422 mW estimated power. These results demonstrate that a compact hardware spike encoder can support multiple spike encoding schemes while remaining practical for lower-power neuromorphic edge systems.
URL: https://digitalcommons.calpoly.edu/eesp/710
Included in
Electronic Devices and Semiconductor Manufacturing Commons, VLSI and Circuits, Embedded and Hardware Systems Commons