Department - Author 1
Electrical Engineering Department
Degree Name - Author 1
BS in Electrical Engineering
Date
6-2016
Primary Advisor
Vladimir Prodanov
Abstract/Summary
The project outlined in this report is the design, layout, and routing of a linear voltage regulator using Cadence VLSI (very-large-scale integration) software. The design specifications for this regulator are as follows: input voltage range of 5V + 1V, load current capabilities of 150mA, and output voltage range of 1.15V to 3.3V. Furthermore, the design of this circuit was broken into three main sub-circuits: an error amplifier, bandgap reference circuitry, and biasing circuitry for the bandgap. Together, these sub-circuits integrated to make the final design.
Research for different topologies for a voltage regulator was done and the Brokaw bandgap reference circuit by Paul Brokaw was used for the reference voltage.
The layout and routing of these sub-circuits was performed by breaking these sub-circuits into even smaller sub-circuits and routing these individually. In the end, the group was able to layout and route all of the sub-circuits. However, several DRC and LVS errors were encountered throughout the layout process. Main sources of errors were due to the bipolar junction transistors and resistors used in this design.
To the best knowledge of the group, layout and routing of the bipolar junction transistors used in this design have never been attempted at California Polytechnic State University San Luis Obispo. Therefore, it was expected that the group ran into several problems with these devices and it is outlined in the report how some of these problems were resolved.
From the final design, it was found that the voltage regulator that was created in Cadence has an output voltage of about 3.4V; 100mV more than the intended 3.3V, yielding a discrepancy of 3% from the design specifications. In regards to temperature, the design deviates about 85mV across the industrial temperature range of -40℃ to 100℃. Another metric that was used to test the final design is the voltage deviation when the load current is swept from 0-150mA,which was found to be 170mV.
It was found that the subcircuits created for this project performed fairly close to the intended purpose and therefore the design of the voltage regulator is seen as a success. Thus, the next step for this project will be to fix the DRC and LVS errors associated with BJTs and resistors. After that, extraction of the circuit should be done to determine the parasitic capacitance and inductance associated with this circuit. And finally, the GDSII file should be made to be sent to the chip manufacturer to tape-out the chip.
URL: https://digitalcommons.calpoly.edu/eesp/348