Available at: https://digitalcommons.calpoly.edu/theses/2989
Date of Award
5-2025
Degree Name
MS in Electrical Engineering
Department/Program
Electrical Engineering
College
College of Engineering
Advisor
Taufik
Advisor Department
Electrical Engineering
Advisor College
College of Engineering
Abstract
With the steep rise in AI-powered workloads, the power requirements for datacenter and enterprise applications have increased rapidly. In these applications, very efficient DC-DC converters are crucial for providing a regulated voltage to processors, memory, and other components from a higher voltage backplane. Increasing power demands put heightened emphasis on the efficiency of voltage step-down solutions, as even small improvements add up to substantial cost savings at the facility scale. This thesis analyzes a new topology for step-down converters, targeting high step-down ratios and large output current requirements. Starting with mathematical derivations, the transfer function, component sizing equations, component rating equations, and details of the circuit’s operation are explored. Simulation is then used to verify the mathematical derivations and understand the nuances of the circuit’s operation. Finally, 12V to 1V 30W hardware prototypes are constructed for the proposed High-Step Down (HSD) converter, and a synchronous buck converter to provide a comparative analysis of their performances. Test results show that the proposed HSD converter yields larger efficiency at full load and cooler board operation than those of the synchronous buck. Overall, the results demonstrate the potential of the proposed HSD topology for use in high step-down ratio and high-power applications.