Available at: https://digitalcommons.calpoly.edu/theses/24
Date of Award
MS in Electrical Engineering
The power requirements for the microprocessor have been increasing as per Moore's Law. According to International Technology Roadmap (ITRS), the Voltage Regulator Module (VRM) for the microprocessor will be 200 W(with 1V, 200A output) in 2010. With the VRMs topology of synchronous buck, serious technical challenges such as small duty cycle, high switching frequencies, and higher current demands, contribute to decreased power density and increased cost. This thesis proposes a Multiphase Multi-Interleave Buck topology to solve the technical challenges of powering future microprocessors. The critical design parameter values are selected using the theoretical design equations and calculations. The design is simulated in OrCAD Pspice to evaluate the performance criteria of the VRM. A prototype of four-phase Multiphase Multi-Interleave Buck Converter is constructed. The critical performance parameters of the prototype are tested and measured. The thesis concludes with the performance of the prototype as compared with the performance of the design simulation.