Design and Characterization of 15nm FinFET Standard Cell Library

Phanindra Datta Sadhu, California Polytechnic State University, San Luis Obispo


The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the breakdown of the transistor caused by short channel effects. Alternative solution to this is the FinFET transistor technology where the gate of the transistor is a 3D fin which surrounds the transistor and prevents the breakdown caused by scaling and short channel effects. FinFET devices are reported to have excellent control over short channel effects, high On/Off Ratio, extremely low gate leakage current and relative immunization over gate edge line roughness. Sub 20 nm is perceived to the limit of scaling the CMOS transistors but FinFETs can be scaled down further due the above-mentioned reasons. Due to these advantages the VLSI industry have now shifted to FinFET in their designs. Although these transistors have not been completely opened to academia. Analyzing and observing the effects of these devices can be pivotal in gaining an in depth understanding of them.

This thesis explores the application of FinFETs using a standard cell library developed using these transistors and are analyzed and compared with CMOS transistors. The FinFET package files used to develop these cell is a 15nm FinFET technology file developed by NCSU in collaboration with Cadence and Mentor Graphics. Post design the cells were characterized and then the results were compared to through various CMOS packages to understand and extrapolate conclusions on the FinFET devices.