Electrical Engineering Department
BS in Electrical Engineering
The Eulerian Video Amplification algorithm developed at MIT allows for amplification of very small changes in seemingly static video scenes. The algorithm helps visualize these small changes by amplifying them to pull out signals of interest, such as the human pulse and the motion of hot air. This algorithm is computationally intensive and, as is, is difficult to run in real-time as a serially executed program. Our project is to design a parallel processing circuit that allows the algorithm to be calculated in hardware in order to magnify these small changes in real time. This will be done by using a highly parallel circuit for computing a Gaussian Pyramid Reduction calculation. The main advantage of a hardware solution is that we can exploit parallelism in order to calculate multiple parts of the algorithm at once, rather than having to perform thousands of calculations in sequence. Unlike previously attempts to develop software methods make to run the algorithm run in real-time, a highly parallel hardware solution allows us to not only run faster, but also save all the intermediate calculations thereby allowing better detection and amplification. The circuit is built to intake a frame of 32 x 32 pixels, and undergo 5 reductions before producing a single reduced pixel that is used in the amplification calculation. Due to multiple issues we had using Cadence we were able to simulate, but not synthesize our Verilog blocks. Unfortunately we could not obtain any timing diagrams or test bench results but, assuming a clock speed of 16MHz and the worst case scenario where only 1 calculation is performed per cycle, the total time from inputting a 32 x 32 frame to receiving an amplified frame out is about .00477 seconds. Since most cameras record at a rate of 60Hz, which equates to .0167 seconds per frame, we are well within the margins needed to be considered “real time” because we can calculate the amplified frame about 3 times faster than the camera can record. Unfortunately, doubling the size of a side of each frame increases computation time nearly 4 fold. This means that, assuming a lock speed of 16MHz and worst case scenario computation time, our circuit could not longer perform in real time if the frame size was increased to 64 x 64 pixels.
Available for download on Tuesday, December 14, 2021