Postprint version. Published in 20th IEEE International Conference on Application-Specific Systems, Architecture and Processors, 2009 Proceedings: Boston, MA, July 7, 2009, pages 75-82.
NOTE: At the time of publication, the author Bridget Benson was not yet affiliated with Cal Poly.
The definitive version is available at https://doi.org/10.1109/ASAP.2009.38.
This paper presents a parallelized architecture of multiple classifiers for face detection based on the Viola and Jones object detection method. This method makes use of the AdaBoost algorithm which identifies a sequence of Haar classifiers that indicate the presence of a face. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing of classifiers, and parallel processing of multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the parallelized architecture which can be scalable for configurable device with variable resources. We implement the proposed architecture in Verilog HDL on a Xilinx Virtex-5 FPGA and show the parallelized architecture of multiple classifiers can have 3.3times performance gain over the architecture of a single classifier and an 84times performance gain over an equivalent software solution.
Electrical and Computer Engineering
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