Recommended Citation
Postprint version. Published in 2010 18th IEEE Annual International Symposium on Field- Programmable Custom Computing Machines (FCCM) Proceedings: Charlotte, NC, May 2, 2010, pages 29-32.
NOTE: At the time of publication, the author Bridget Benson was not yet affiliated with Cal Poly.
The definitive version is available at https://doi.org/10.1109/FCCM.2010.50.
Abstract
This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times performance improvement over an equivalent software solution and 1.9 times performance improvement over the leading hardware color classifier.
Disciplines
Electrical and Computer Engineering
Copyright
2010 IEEE.
Publisher statement
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URL: https://digitalcommons.calpoly.edu/eeng_fac/250