Published in Proceedings of the 2001 IEEE Custom Integrated Circuits Conference: San Diego, CA, May 6, 2001, pages 497-500.
NOTE: At the time of publication, the author Vladimir Prodanov was not yet affiliated with Cal Poly.
The definitive version is available at https://doi.org/10.1109/CICC.2001.929829.
This paper describes high-voltage CMOS buffer architecture that uses low-voltage transistors. The voltage capability of the presented architecture is nearly three times larger than the voltage capability of the used MOSFET's. This buffer topology could be used to provide 3.3 V compatibility of 1.2 V and 1.5 V digital ICs implemented in standard CMOS technology. A 7 V circuit-prototype was fabricated in 0.25 /spl μ/m 2.5 V CMOS technology. Performed measurements demonstrate stress-free operationin both active and high-impedance mode.
Electrical and Computer Engineering
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