College - Author 1
College of Engineering
Department - Author 1
Computer Engineering Department
Degree Name - Author 1
BS in Computer Engineering
Joseph Callenes-Sloan, College of Engineering, Computer Engineering Department
This project is a debugger and programmer for the OTTER CPU, the implementation of the RISC-V ISA used by Cal Poly to teach computer architecture and assembly language in CPE 233/333 and usually implemented on the Basys3 FPGA development board. With this tool, students can quickly program their OTTER with a new/revised RISC-V program binary without resynthesizing the entire FPGA design. They can then use the debugger from a PC to pause/continue/single-step execution and set breakpoints, while inspecting and modifying register and memory contents. This enables real-time debugging of OTTER projects involving custom hardware such as a keyboard and VGA monitor, previously unavailable to students. Future work will integrate this debugger with GDB to enable powerful debugging within a graphical IDE.