Author(s) Information

Riley C. OlsonFollow


College of Engineering


Computer Engineering Department

Degree Name

BS in Computer Engineering




Joseph Callenes-Sloan


As time goes on, computers become more and more powerful. However, as processing time becomes less of a limiting factor for computing tasks, power consumption takes its place for many tasks. This paper proposes and tests a new method for sorting analog signals. This new sorting method converts analog signals into Pulse Width Modulated(PWM) signals of varying duty cycle , which are then sorted by a simple network of combinational logic, and then converted to a normal binary representation. In order to implement this new method, multiple circuits had to be designed and and tested to ensure their functionality and power efficiency. Three circuits total were designed to convert analog voltages into variable duty cycle PWM signals, to sort the PWM signals, and to convert the PWM signals into a binary representation. Simulations of these circuits were tested in LTspice and Vivado to confirm their functionality and determine their power consumption. The simulation data was compared with power dissipation data for a standard Analog to Digital conversion and comparison-based sorting algorithm. The new method proposed in this paper provides an improvement in energy efficiency over the latter method, and can be used as a more efficient method of converting and sorting data received from analog sensors.

Available for download on Saturday, June 15, 2019