College - Author 1
College of Engineering
Department - Author 1
Computer Engineering Department
Degree Name - Author 1
BS in Computer Engineering
Date
6-2018
Primary Advisor
Tina Smilkstein, College of Engineering, Electrical Engineering Department
Abstract/Summary
This paper seeks to describe the process of developing a new FPGA architecture from nothing, both in terms of knowledge about FPGAs and in initial design material. Specifically, this project set out to design an FPGA architecture which can implement a simple state machine type design with 10 inputs, 10 outputs and 10 states. The open source Verilog-to-Routing FPGA CAD flow tool was used in order to synthesize, place, and route HDL files onto the architecture. This project was completed in terms of the spirit of the original goals of implementing an FPGA from scratch. Although, the project resulted in an architecture which slightly underperformed in its ability to route 100% of 10 input, 10 output, 10 state designs due to the general place and route algorithm used and the lack of non-contrived 10 input 10 output 10 state FSM designs.
URL: https://digitalcommons.calpoly.edu/cpesp/259