Computer Engineering Department
BS in Computer Engineering
Simulations have long been a part of the engineering process in both the professional and academic domain. From a pedagogic standpoint, simulations allow students to explore the dynamics of engineering scenarios by controlling variables, taking measurements, and observing behavior which would be difficult or impossible without simulation. One such tool is a CPU simulator used in Cal Poly’s Computer Architecture classes; this software simulates an instruction accurate operation of a computer processor and reports statistics regarding the execution of the supplied compiled machine code. For the last several years Cal Poly’s computer architecture classes have used a previous version of the CPU simulator that simulated the MIPS architecture. Although the previous system was a functional and useful tool, it had significant room for improvement. Although it was once common, the MIPS architecture is much relevant in industry today, especially in the face of its current competitors. From a technical standpoint the MIPS architecture is very similar to other common RISC architectures, but as current technology evolves the usefulness of a MIPS simulator in helping students understand the operation of modern CPUs will continue to diminish. Another place for improvement was in the design of the simulator itself. Since class assignments involving the CPU simulator often require the students to modify an intentionally incomplete version of the simulator, students must also understand the design of the simulator software itself. Though it is functional, the design of the MIPS simulator was minimally documented and the logical organization of the code obfuscates the system being simulated. This has been a source of frustration for not only students, but also for the professors who teach the courses in which the simulator is used. I sought to address these problems in 2 fundamental ways: first, by migrating the simulation to the ARMv7-A architecture and secondly, by doing a complete structural redesign of the simulator as to make the simulation architecture as transparent as possible vis-à-vis the architecture being simulated.