Degree Name

BS in Materials Engineering


Materials Engineering Department


Richard Savage


An electrostatically actuated silicon membrane was designed and fabricated utilizing a siliconon- insulator wafer. The SOI wafer contains three layers- a 400μm thick “handle” layer of silicon followed by a 2μm thick oxide layer topped with a 20μm thick “device” layer of silicon. The embedded oxide layer acts as an etch-stop during silicon etching, leaving a thin membrane of consistent thickness on the device side. The device dimensions were chosen to provide acceptable membrane deflection predicted by calculations and Finite Element Analysis. A microfabrication process plan was designed to produce thin membranes appropriate for electrostatic actuation. A 700nm layer of silicon dioxide was grown on both sides of the SOI wafer to be used as a mask during silicon etching. The handle side of the SOI wafer was coated with positive photo resist and the wafer was patterned through lithography using a measured light integral of 4. Following lithography, the exposed silicon dioxide on the handle side was etched with a buffered oxide etch, leaving regions of exposed silicon on the handle. The entire wafer was then placed in tetramethylammonium hydroxide at 85°C to etch through the 400μm of exposed silicon on the handle. Previous experiments with TMAH gave an average etch rate of 35μm/s for silicon. The TMAH etch was stopped by the imbedded layer of silicon dioxide, leaving the 22μm thick silicon membranes. Finally, the remaining silicon dioxide was removed with another buffered oxide etch. The final etch depth was measured with a profilometer.