United States Patent Number: 6,610,150, August 26, 2003. 27 pages. Also available from the United States Patent and Trademark Office. Website: http://www.uspto.gov.
NOTE: At the time of publication, the author Richard Savage was not yet affiliated with Cal Poly.
A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.
Materials Science and Engineering