Industrial and Manufacturing Engineering

The Morphology Evolution and Voiding of Solder Joints on QFN Central Pads with a Ni/Au Finish

Julie Silk et al. — Mon, 12 Mar 2012 13:40:15 PDT

In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish. Samples were isothermally aged at the equivalent of 0, 2, 7 and 14 years service life. Representative solder joints were cross-sectioned and analyzed using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX) in order to investigate the evolution of the solder joint morphology as a function of Au content and isothermal aging. IMC thickness was measured. The effect of Au content on the void percentage was studied as well. The results show that if copper is available to dissolve into the solder joint, the AuSn₄ IMC from the bulk does not migrate to the interface as a result of thermal aging. The IMC thickness grew with aging as expected, however with Cu base metallization the IMC was dominated by Cu₆Sn₅, and with Ni base metallization on both sides of the joint the IMC was dominated by AuSn₄. Voiding analysis showed that thick Au metallization on thermal pads leads to more voiding and larger standoff height.

The Limits of Reflexive Design in a Secrecy-Based Organization

Michael W. Stebbins et al. — Wed, 07 Dec 2011 11:38:38 PST

Effect of Gold Content on the Reliability of SnAgCu Solder Joints

Jianbiao Pan et al. — Thu, 01 Dec 2011 10:47:33 PST

Electroplated Ni/Au over Cu is a popular metallization for printed circuit board finish as well as for component leads, especially wire-bondable high-frequency packages, where the gold thickness requirement for wire bonding is high. The general understanding is that less than 3 wt% of Au is acceptable in SnPb solder joints. However, little is known about the effect of Au content on the reliability of SnAgCu solder joints. The purpose of this paper is to determine the acceptable level of Au in SAC305 solder joints. Three different package platforms with different Au thicknesses were assembled on boards with two different Au thicknesses using a standard surface mount assembly line in a realistic production environment. The assembled boards were divided into three groups: as-built, isothermally aged at 125 ^°C for 30 days, and isothermally aged at 125 ^°C for 56 days. All boards were then subjected to accelerated mechanical reliability tests including random vibration and drop testing. The results show that solder joints with over 10 wt% Au are unacceptable. If Cu is available to dissolve in the solder joint, then an Au content under 5 wt% will not significantly degrade the reliability of the solder joint. When Ni layers are present on both the board and the component sides of the interface, this limits the ability of Cu to dissolve into the solder joint, and hence an Au content under 3 wt% is acceptable. The failure mechanism for solder joints with high Au content is fractures through the AuSn₄ intermetallic compound. Additional findings confirmed that there is a danger of placing parts near high-stress areas and that a high level of voiding reduced reliability.

A Study of Solder Joint Failure Criteria

Jianbiao Pan et al. — Fri, 04 Nov 2011 15:43:09 PDT

One of the challenges in an experimental study of solder joint reliability is to determine when cracks occur in a solder joint or when a solder joint fails. Cracks in a real solder joint are difficult to identify using an X-Ray system. Cross-sectioning and scanning electron microscopy (SEM) is a destructive method. A common non-destructive test method is to monitor resistance increase in a solder joint or a daisy-chain. However, no scientific research has been done in establishing the relationship between the crack area of an interconnection and the change in resistance of the interconnection. This paper proposes a method of defining failure criteria as the resistance increase in a solder joint exceeding a threshold. The threshold is determined by k times the range over the natural variation in resistance measured by a measurement system. The natural variation by random cause is judged using X-bar and R charts. The principles of defining failure criteria are to be able to detect failure of solder joints as early as possible with minimum false detection due of measurement system error/variation. An experimental study confirmed that a full crack of an interconnection occurs when the increase of resistance in the interconnection is 10 times the natural variation of resistance change. The results of this study could be used to narrow the definition of failure in consensus standards IPC 9701A, JESD22-B111, and IPC/JEDEC-9702.

Effect of Gold Content on the Microstructural Evolution of SAC305 Solder Joints Under Isothermal Aging

Mike Powers et al. — Fri, 04 Nov 2011 15:43:02 PDT

Au over Ni on Cu is a widely used printed circuit board (PCB) surface finish, under bump metallization (UBM), and component lead metallization. It is generally accepted that less than 3 wt.% Au in Sn-Pb solder joints inhibits formation of detrimental intermetallic compounds (IMC). However, the critical limit for Au content in Pb-free solder joints is not well established. Three surface-mount package platforms, one with a matte Sn surface finish and the others with Ni/Au finish, were soldered to Ni/Au-finished PCB using Sn-3.0Ag- 0.5Cu (SAC305) solder, in a realistic manufacturing setting. The assembled boards were divided into three groups: one without any thermal treatment, one subjected to isothermal aging at 125^oC for 30 days, and the third group aged at 125^oC for 56 days. Representative solder joints were cross-sectioned and analyzed using scanning electron microscopy (SEM) and energy-dispersive x-ray spectroscopy (EDX) to investigate the evolution of the solder joint morphology as a function of Au content and isothermal aging. It was found that, if Cu is available to dissolve in the solder joint, the migration of AuSn₄ from the bulk to the interface as a result of thermal aging is mitigated.

On Capacity Modeling for Production Planning with Alternative Machine Types

Robert C. Leachman et al. — Fri, 30 Sep 2011 13:35:04 PDT

Analyzing the capacity of production facilities in which manufacturing operations may be performed by alternative machine types presents a seemingly complicated task. In typical enterprise-level production planning models, capacity limitations of alternative machine types are approximated in terms of some single artificial capacitated resource. In this paper we propose procedures for generating compact models that accurately characterize capacity limitations of alternative machine types. Assuming that processing times among alternative machine types are identical or proportional across operations they can perform, capacity limitations of the alternative machine types can be precisely expressed using a formulation that is typically not much larger than the basic linear programming formulation that does not admit alternative resource types. These results have important implications for industrial practice, suggesting that in the case that processing times are nearly proportional among alternatives, the prevalent approximation that involves using a single, capacitated, artificial resource may be dropped in favor of our formulation incorporating the approximation that processing times among the alternatives are proportional. Another advantage is that the set of capacity constraints we formulate can be used to check the feasibility of suggested production schedules or demands simply by plugging them into the constraints, without need to develop values for allocation variables.

Proposed Scheduling Methods for Printed Circuit Board Assembly

Tali Freed et al. — Fri, 30 Sep 2011 13:34:49 PDT

The current practice in the assembly of electronic components on printed circuit boards (PCB's) is serial production, a process characterized by very long set-up times.

However. with the advent of efficient on-line process information, new production control methods are now possible. This paper proposes two new production methods - the Grouped Set-up (GSU) method and the Sequence-Dependent Scheduling (SDS) method, which can significantly reduce set-up times.

It is shown that the GSU always performs better than the SDS method in terms of total production flow (throughput). while the SDS performs better than the GSU method in terms of work-in-process (WIP) inventory.

Group set-up for printed circuit board assembly

Tali F. Carmon et al. — Fri, 30 Sep 2011 13:34:46 PDT

The current practice in the assembly of electronic components on printed circuit boards (PCBs) is serial production. a process characterized by very long set-up times. However, with the advent of efficient on-line process information .. new production control methods are now possible. This paper proposes a different production method, called the group set-up (GSU) method, which can significantly reduce set-up times. The traditional and the GSU production methods are compared, and it is shown that the GSU always performs better than the traditional method in terms of total production flow (throughput) and labour time However, the traditional method performs better than the GSU in terms of work in process (WIP) inventory; and in some cases, in terms of makespan (lead time). A detailed analysis for a small number of PCBs is presented.

Set-up saving schemes for printed circuit boards assembly

Oded Z. Maimon et al. — Fri, 30 Sep 2011 13:34:39 PDT

Focusing on a basic printed circuit board (PCB) assembly line configuration characterized by very long set-up times, we examine two scheduling methods that can significantly reduce the set-up. Both methods -the Grouped Set-Up (GSU) method that has been recently introduced in the literature and the Sequence Dependent Scheduling (SDS) method, which has not been studied in this context -are based on component commonality among PCB types. Using the typical traditional scheduling method as a benchmark, the GSU and the SDS methods are compared in terms of three performance measures: line throughput, average work-in-process (WIP) inventory level, and implementation complexity. Guidelines for selecting the most appropriate method for a given production environment are proposed. The analysis is illustrated using real data from a typical production line.

A preliminary model for lot sizing In semiconductor manufacturing

Tali F. Carmon et al. — Fri, 30 Sep 2011 13:34:35 PDT

A Psychological Perspective on Service Segmentation Models: The Significance of Accounting for Consumers' Perceptions of Waiting and Service

Ziv Carmon et al. — Fri, 30 Sep 2011 13:34:29 PDT

We examine how service should be divided and scheduled when it can be provided in multiple separate segments. We analyze variants of this problem using a model with a conventional function describing the waiting cost, that is modified to account for some aspects of the psychological cost of waiting in line. We show that consideration of the psychological cost can result in prescriptions that are inconsistent with the common wisdom of queuing theorists derived according to the conventional approach (e.g., equal load assignments). More generally, our intention in this paper is to illustrate that aspects of the psychological cost of waiting can be accounted for in the analysis of queuing systems, and that this may have significant implications for the service schemes that are derived.

Scheduling Semiconductor Device Test Operations on Multihead Testers

Tali Freed et al. — Fri, 30 Sep 2011 13:34:25 PDT

Past attempts to devise scheduling methods for the device test operations of semiconductor manufacturing firms fail to address a significant characteristic of multiple-head test systems—the dependency of processing rates on the lots processed simultaneously on the testers. Since the problem has never been modeled accurately in the scheduling literature, feasibility and performance of previously proposed scheduling methodologies for multihead testers may not be accurately assessed. In this paper, we describe the multihead tester scheduling problem, present an enumeration solution procedure, and illustrate the problems of previously suggested tester scheduling algorithms.

A Taxonomy of Scheduling Problems in Semiconductor Device Test Operations

Tali Freed et al. — Fri, 30 Sep 2011 13:34:21 PDT

Semiconductor device test facilities differ not only by production volume and tester brands. The complexity of the devices and the characteristics of the testers affect the scheduling methodologies as well. Goals and strategies vary from one firm to another, leading to a variety of objectives and performance measures. Due to random yield lot size is variable and lot priorities are common. Changeover times are oftentimes sequence-dependent. Since semiconductor device testing systems are very costly, scheduling methods that increase the throughput of the facility are financially significant. In this paper we describe a variety of semiconductor device testing environments, develop mathematical formulations for their scheduling problems, and suggest solution methods. The paper is intended to serve as a basis for the development of scheduling systems for a variety of semiconductor device testing facilities.

Work Flow Policy and Within-Worker and Between-Workers Variability in Performance

Kenneth Howard Doerr et al. — Fri, 30 Sep 2011 13:34:12 PDT

Work flow policies are shown to induce a change in average between-workers variability (worker heterogeneity) and within-worker variability in performance times. In a laboratory experiment, the authors measured the levels of worker heterogeneity and within-worker variability under an individual performance condition, a work sharing condition, and a fixed assignment condition. The work sharing policy increased the levels of worker heterogeneity and worker variability, whereas the fixed assignment policy decreased them. These effects, along with work flow policy main effects on mean performance times and variability are examined. This article represents an initial step in understanding effects that may be important in the selection of an operating policy, the ignorance of which may lead to costly misestimates of performance.

The Benefits of Automatic Data Collection in the Fresh Produce Supply Chain

Ryan Charles Panos et al. — Fri, 30 Sep 2011 13:34:10 PDT

The potential for RFID based systems to improve the safety and efficiency of a supply chain with rapidly decaying products and strict health standards is creating pressure to adopt RFID in several agricultural industries. A handful of fresh produce industry leaders currently participate in mandated pilot projects, while the industry as a whole is still intimidated by the perceived cost of RFID. Therefore in this study we attempt to validate the correlation between performance and automated data collection, paving the way to economic justification of investment in data collection technologies, such as barcode and RFID.

The majority of product in this industry is identified and tracked using pallet barcode labels at the more progressive facilities, or facility-specific manual identification methods at the less advanced facilities. Most fresh produce facilities in the US have minimal information systems capabilities, and most of their logistics operations are documented on paper only.

Thus the form of Automated Data Collection (ADC) used in the more advanced facilities is Barcode-based. This study compares facilities that use ADC with those that do not. Significant advantages of using ADC are found in many areas, especially in product spoilage, administrative labor and space utilization.

In-house development of scheduling decision support systems: case study for scheduling semiconductor device test operations

Tali Freed et al. — Fri, 30 Sep 2011 13:34:05 PDT

Most manufacturing processes can benefit from an automated scheduling system. However;: the design of a fast, computerised scheduling system that achieves high-quality results and requires minimal resources is a difficult undertaking. Efficient .. scheduling of a semiconductor device test facility requires an information system that provides good schedules quickly. Semiconductor device testing-is the last stage of the long semiconductor manufacturing process, and therefore. is subjected to customer service pressures. The cost of an off-the-shelf computerised scheduling system may he prohibitive for many companies. In addition, many companies are taken aback by other characteristics of off-the-shelf scheduling systems, such as code confidentiality, maintenance costs, and failure rates. We draw upon the literature and our field case to discuss some of the"trade-offs bet\',:een in-house development and off-the-shelf acquisition of software: We describe the in-house design and implementation of a scheduling decision :support system for one device test facility. Using the design and implementation process of this system as a case study, we discuss how one facility uses in-house design of systems in a strategic way, as a competitive capability.

Effect of Gold Content on the Reliability of SnAgCu Solder Joints

Jianbiao Pan et al. — Mon, 01 Aug 2011 14:14:18 PDT

Electroplated Ni/Au over Cu is a popular metallization for PCB finish as well as for component leads, especially wire-bondable high frequency packages, where the gold thickness requirement for wirebonding is high. The general understanding is that less than 3 wt% of Au is acceptable in SnPb solder joints. However, little is known about the effect of Au content on the reliability of SnAgCu solder joints. The purpose of this study is to determine the acceptable level of Au in SAC305 solder joints. Three different package platforms with different Au thicknesses were assembled on boards with two different Au thicknesses using a standard surface mount assembly line in a realistic production environment. The assembled boards were divided into three groups: as-built, isothermally aged at 125°C for 30 days, and isothermally aged at 125°C for 56 days. All boards were then subjected to accelerated mechanical reliability tests including random vibration and drop testing. The results show that solder joints with over 10 wt% Au are unacceptable. If Cu is available to dissolve in the solder joint, then an Au content under 5 wt% will not significantly degrade the reliability of the solder joint. When Ni layers are present on both the board and component sides of the interface, this limits the ability of Cu to dissolve into the solder joint and hence an Au content under 3 wt% is acceptable. The failure mechanism for solder joints with high Au content is fractures through the AuSn₄ IMC. Our comprehensive long-term reliability study did not confirm the finding by Ho et al. (2002) that the weak interface between (Au, Ni)Sn₄ and Ni₃Sn₄ results in brittle interfacial failure. Additional findings confirmed the danger of placing parts near high stress areas and that a high level of voiding reduced reliability.

Development and Assessment of a PCB Layout and Manufacturong Laboratory Module in Introductory Electric Circuits for EE and Non-EE Majors

Albert Liddicoat et al. — Tue, 12 Oct 2010 11:53:12 PDT

In standard introductory electric circuits laboratories for electrical engineering (EE) majors and non-EE majors, prototype boards are typically used to construct and test electric circuits. Students typically do not learn how to design and manufacture Printed Circuit Boards (PCB) that are commonly used in more sophisticated design projects and other engineering applications. This paper will present the development and assessment of a PCB layout and manufacturing laboratory module that has been used in introductory electric circuits laboratories for EE and non-EE majors. The feasibility of integrating the new PCB layout and manufacturing module into the electric circuit course will be discussed. An experiment has been designed and conducted to assess the impact of the PCB module. A survey with questions from the Motivated Strategies for Learning Questionnaire (MSLQ) supplemented with additional questions was used to measure students’ motivation and the impact of the PCB module on student learning. In Winter quarter of 2009 at Cal Poly, two lab sessions for sophomore and junior non-EE engineering majors were taught by an instructor with an experimental group that designed a real PCB for one of their circuit design experiments and a control group that implemented all of the experiments using prototype boards. In Spring quarter of 2009 at Cal Poly, two lab sessions for EE majors at the sophomore level were offered by the same instructor with an experimental group that designed and built a PCB for one of their circuit design experiments and a control group that performed all experiments using prototype boards. Data have been collected and analyzed for these four student groups. Results indicate the inclusion of the PCB module did not impact the student’s ability to achieve any of the course or laboratory learning objectives. Though no statistically significant difference in student’s motivation was found between the experimental group and the control group, the results strongly indicate that students enjoyed the introduction of the PCB design module. Furthermore, students report they have a higher confidence in their ability to design printed circuit boards and they are more likely to design PCBs in other course projects as part of their senior projects.

Assessing Curriculum Improvement Through Senior Projects

Jianbiao Pan et al. — Tue, 12 Oct 2010 11:53:11 PDT

Senior project and/or capstone design courses are intended to provide a culminating design experience for students and to demonstrate their understanding of engineering knowledge and their ability to apply that knowledge to practical problems. It is expected that the quality and attributes of students’ senior design projects can be used as a good measure of determining how well the curriculum prepares students to engage in engineering design as well as a measure of faculty teaching and student learning. This paper reports the results of a study designed to assess whether the new computer engineering curriculum implemented at Cal Poly over the previous five years has had a positive impact in preparing students for engineering design through measuring the quality and complexity of senior design projects. A randomized complete block design was used in the study. Ten senior projects each were randomly selected from the population of three groups: computer engineering senior projects completed in the 2002-2003 academic year, computer engineering senior projects completed in the 2007-2008 academic year, and electrical engineering senor projects completed in the 2007-2008 academic year. A senior project evaluation rubric was developed to assess the quality and complexity of the senior projects. Members from the Computer Engineering Industrial Advisory Board used the rubric to score the randomly selected senior projects. The scores assigned by the advisory board members were compared to the letter grades assigned by faculty advisors for these senior projects. The results of the analysis show that the overall quality of computer engineering senior projects improved from academic year 2002-2003 to academic year 2007-2008. However, there is a statistically significant difference in the overall senior project grades assigned between faculty advisors as compared to senior project scores assigned by the advisory board members. The results also indicate that the rubric developed from this study is robust since different evaluators did not have a statistically significant effect on the grading of senior projects.

The Effect of Ultrasonic Frequency on Gold Wire Bondability and Reliability

Jianbiao Pan et al. — Mon, 21 Sep 2009 15:27:08 PDT

This paper presents a systematic study on the effect of 120 KHz ultrasonic frequency on the bondability and reliability of fine pitch gold wire bonding to pads over an organic substrate with gold metallizations. The study was carried out on a thermosonic ball bonder that is allowed to easily switch between ultrasonic frequencies of 60 KHz and 120 KHz by changing the ultrasonic transducer and the ultrasonic generator. Bonding parameters were optimized through the design of experimental methodology for four different cases: 25.4 mm wire at 60 kHz, 25.4 mm wire at 120 kHz, 17.8 mm wire at 60 kHz, and 17.8 mm wire at 120 kHz. The integrity of wire bonds was evaluated by six response variables. The optimized bonding process was selected according to the multiattribute utility theory. With the optimized bonding parameters developed on one metallization for each of the four cases, 8,100 bonds were made on five different metallizations. The samples were then divided into three groups. The first group was subjected to humidity at 85º C/85% RH for up to 1,000 h. The second group was subjected to thermal aging at 125ºC for up to 1,000 h. The third group was subjected to temperature cycling from -55ºC to +125ºC with 1 h per cycle for up to 1,000 cycles. The bond integrity was evaluated through the wire pull and the ball shear tests immediately after bonding, and after each 150, 300, 500, and 1,000 h time interval in the reliability tests. Results show that 120 kHz frequency requires less ultrasonic power than 60 kHz when all other parameters are equal. The results also indicate that bonding at 120 kHz frequency is less sensitive to different metallizations than bonding at 60 kHz. All three reliability tests do not negatively affect the bond integrity of Au wire bonds on a variety of Au metallizations for both frequencies. Furthermore, as the reliability test time increases, both pull and shear strengths of Au wire bonds on Au pads increase.