Recommended Citation
Postprint version. Published in IEEE Transactions on Semiconductor Manufacturing, Volume 12, Issue 4, November 1, 1999, pages 523-530.
Copyright © 1999 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The definitive version is available at http://dx.doi.org/10.1109/66.806130.
NOTE: At the time of publication, the author Tali Freed was not yet affiliated with Cal Poly.
Abstract
Past attempts to devise scheduling methods for the device test operations of semiconductor manufacturing firms fail to address a significant characteristic of multiple-head test systems—the dependency of processing rates on the lots processed simultaneously on the testers. Since the problem has never been modeled accurately in the scheduling literature, feasibility and performance of previously proposed scheduling methodologies for multihead testers may not be accurately assessed. In this paper, we describe the multihead tester scheduling problem, present an enumeration solution procedure, and illustrate the problems of previously suggested tester scheduling algorithms.
Disciplines
Industrial Engineering | Manufacturing
Included in
URL: http://digitalcommons.calpoly.edu/ime_fac/72