Postprint version. Published in IEEE Transactions on Semiconductor Manufacturing, Volume 12, Issue 4, November 1, 1999, pages 523-530.
NOTE: At the time of publication, the author Tali Freed was not yet affiliated with Cal Poly.
The definitive version is available at https://doi.org/10.1109/66.806130.
Past attempts to devise scheduling methods for the device test operations of semiconductor manufacturing firms fail to address a significant characteristic of multiple-head test systems—the dependency of processing rates on the lots processed simultaneously on the testers. Since the problem has never been modeled accurately in the scheduling literature, feasibility and performance of previously proposed scheduling methodologies for multihead testers may not be accurately assessed. In this paper, we describe the multihead tester scheduling problem, present an enumeration solution procedure, and illustrate the problems of previously suggested tester scheduling algorithms.
Industrial Engineering | Manufacturing
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