Postprint version. Published in Proceedings of the International Conference on Modeling and Analysis of Semiconductor Manufacturing, April 1, 2002, pages 252-259.
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NOTE: At the time of publication, the author Tali Freed was not yet affiliated with Cal Poly.
Semiconductor device test facilities differ not only by production volume and tester brands. The complexity of the devices and the characteristics of the testers affect the scheduling methodologies as well. Goals and strategies vary from one firm to another, leading to a variety of objectives and performance measures. Due to random yield lot size is variable and lot priorities are common. Changeover times are oftentimes sequence-dependent. Since semiconductor device testing systems are very costly, scheduling methods that increase the throughput of the facility are financially significant. In this paper we describe a variety of semiconductor device testing environments, develop mathematical formulations for their scheduling problems, and suggest solution methods. The paper is intended to serve as a basis for the development of scheduling systems for a variety of semiconductor device testing facilities.
Industrial Engineering | Manufacturing