Date

6-2011

Degree Name

BS in Electrical Engineering

Department

Electrical Engineering Department

Advisor

Vladimir Prodanov

Abstract

This project demonstrates the error mitigating effects of using a three-level “smooth ternary” signal on a Deep-Submicron(DSM) bus with large inter-wire capacitance. An RC circuit used to simulate and exaggerate (for easier testing) the charging and discharging of the DSM bus. An encoder stage translates binary input data into a three-level signal before sending it to the bus. A decoder stage then translates the three-level signal back to binary that is ideally identical to the original signal. Our results show that the three-level signal has much cleaner transitions than a traditional binary signal. A few glitches that appeared when decoding the ternary signal back to binary can be addressed and fixed in future iterations of the design