Recommended Citation
Postprint version. Published in Wireless Communications and Networking Conference, 2009 Proceedings: Budapest, Hungary, April 5, 2009, pages 1-6.
Copyright © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The definitive version is available at http://dx.doi.org/10.1109/WCNC.2009.4917602.
NOTE: At the time of publication, the author Bridget Benson was not yet affiliated with Cal Poly.
Abstract
Matrix decomposition is required in various algorithms used in wireless communication applications. FPGAs strike a balance between ASICs and DSPs, as they have the programmability of software with performance capacity approaching that of a custom hardware implementation. However, FPGA architectures require designers to make a countless number of system, architectural and logic design decisions. By performing design space exploration, a designer can find the optimal device for a specific application, however very few tools exist which can accomplish this task. This paper presents automatic generation and optimization of decomposition methods using a core generator tool, GUSTO, that we developed to enable easy design space exploration with different parameterization options such as resource allocation, bit widths of the data, number of functional units and organization of controllers and interconnects. We present a detailed study of area and throughput tradeoffs of matrix decomposition architectures using different parameterizations.
Disciplines
Electrical and Computer Engineering
URL: http://digitalcommons.calpoly.edu/eeng_fac/255