Title
Performance Study of Power Factor Correction Circuits
Recommended Citation
Published in International Conference on Electrical Engineering and Informatics Proceedings: Bandung, Indonesia, January 1, 2007.
Copyright © 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Abstract
As the use of switched mode power supply (SMPS) has become ever increasingly popular, the importance of implementing power factor correction circuit (PFC) has grown to be crucial. Researchers around the globe have proposed topologies that would produce not only better power factor at the input stage of SMPS but also more energy efficient. While these efforts are needed and necessary to prepare for future challenges in SMPS, the fact is in many of SMPS produced today, power factor correction circuit is not yet required to be embedded in them. Therefore, one way to promote awareness of the importance of PFC circuit to manufacturers, utilities, and more importantly consumers is to show them empirically the staggering benefits of using the circuit in SMPS. This paper is aimed to show the astounding improvement in power factor at the input stage of the SMPS with the use of boost-converter-based PFC circuit. To appreciate the benefit, input power factor performance and efficiency of SMPS with PFC circuit will be compared to other commonly used passive circuits located at the input stage of SMPS. Computer simulations, laboratory setup as well as results of the experiment will be described in this paper
Disciplines
Electrical and Computer Engineering
URL: http://digitalcommons.calpoly.edu/eeng_fac/210