United States Patent Number: 6,211,717, April 3, 2001. 8 pages. Also available from the United States Patent and Trademark Office. Website: http://www.uspto.gov.
NOTE: At the time of publication, the author Vladimir Prodanov was not yet affiliated with Cal Poly.
A multiple differential pair circuit is disclosed having a transconductance, gm, proportional to the bias current, I0, for any transistor technology. The transistors utilized to construct each of the differential transistor pairs in a multiple differential pair circuit operate in a non-exponential voltage-current (V-I) region. As multiple differential pair circuits are linearized, the effective transconductance, gm, becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices. Methods and apparatus are disclosed that provide a linear transconductance, gm, with respect to the bias current, I0, using differential pairs of transistors where each transistor operates in a non-exponential voltage-current (V-I) region, such as MOS transistors.
Electrical and Computer Engineering