United States Patent Number 6,693,469, December 12, 2002. 20 pages. Also available from the United States Patent and Trademark Office. Website: http://www.uspto.gov.
NOTE: At the time of publication, the author Vladimir Prodanov was not yet affiliated with Cal Poly.
An up to 3× breakdown voltage tristate capable integrated circuit CMOS buffer includes a level shifter circuit and a driver circuit. The driver stage includes a series connected n-channel and p-channel cascode stacks, each including at least three transistors. Dynamic gate biasing is provided for the third n-channel and p-channel cascode transistors to prevent voltage overstress of the cascode transistors. The level shifter circuit includes at least one pseudo N-MOS inverter including an input transistor, a protective cascode stack including at least one n-channel cascode transistor, and a load transistor. The level shifter provides at least one voltage shifted input signal to the driver.
Electrical and Computer Engineering