Abstract

The present invention is directed towards a data detector for deriving a data signal from an incoming radio frequency input. The data detector comprises a delay logic which receives an unfiltered signal in quadrature and in-phase components, and applies a delay to each of the in-phase and quadrature phase components of the unfiltered input signal. The detector further comprises a first multiplication logic that multiplies the delayed in-phase component of the unfiltered signal by the quadrature phase component of the unfiltered signal to obtain a first result, and a second multiplication logic that multiplies the delayed quadrature phase component of the unfiltered signal by the in-phase component of the unfiltered signal to obtain a second result. Finally, an adder adds the first result with the second result to generate a data signal. In alternative embodiments a post detection correction algorithm may be added to improve performance.

Disciplines

Electrical and Computer Engineering

Number of Pages

10

Publisher statement

Also available from the United States Patent and Trademark Office. Website: http://www.uspto.gov.

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URL: http://digitalcommons.calpoly.edu/eeng_fac/162