Recommended Citation
Published in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems: Geneva, Switzerland, Volume 5, May 28, 2000, pages 437-440.
NOTE: At the time of publication, the author Vladimir Prodanov was not yet affiliated with Cal Poly.
The definitive version is available at https://doi.org/10.1109/ISCAS.2000.857465.
Abstract
Variation in the “on” resistance of a MOS sampling switch can introduce distortion into the front end of a switched-capacitor filter or analog-to-digital converter. We review three methods commonly used to linearize the resistance of a MOS switch and propose a new technique that addresses their limitations. A practical method for implementation is also suggested.
Disciplines
Electrical and Computer Engineering
Copyright
2000 IEEE.
Publisher statement
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URL: https://digitalcommons.calpoly.edu/eeng_fac/150