Published in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems: Geneva, Switzerland, Volume 5, May 28, 2000, pages 437-440.
Copyright © 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. The definitive version is available at http://dx.doi.org/10.1109/ISCAS.2000.857465.
NOTE: At the time of publication, the author Vladimir Prodanov was not yet affiliated with Cal Poly.
Variation in the “on” resistance of a MOS sampling switch can introduce distortion into the front end of a switched-capacitor filter or analog-to-digital converter. We review three methods commonly used to linearize the resistance of a MOS switch and propose a new technique that addresses their limitations. A practical method for implementation is also suggested.
Electrical and Computer Engineering