Published in IEEE Journal of Solid-State Circuits, Volume 41, Issue 2, February 1, 2006, pages 339-351.
Copyright © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. The definitive version is available at http://dx.doi.org/10.1109/JSSC.2005.862346.
NOTE: At the time of publication, the author Vladimir Prodanov was not yet affiliated with Cal Poly.
We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-μm CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presented
Electrical and Computer Engineering