Title

Logic Tiles

Date

6-2017

Degree Name

BS in Computer Engineering

Department

Computer Engineering Department

Advisor(s)

Andrew Danowitz

Abstract

This project was originally conceived by Professor Andrew Danowitz as he considered the restructuring of the introductory digital design course at Cal Poly. As it stands now, students apply their knowledge of boolean algebra and combinatorial logic through the programming of a Field Programmable Gate Array (FPGA) using a Hardware Descriptive Language (HDL). While this is the industry standard for designing large, complex digital circuits, and is an fundamental skill to learn, there is a lack of actual circuit building in the process that can cause a disconnect from theory to application for students who have little-to-no experience with digital logic. Our project attempts to bridge that gap by providing a physical device with which students can manually develop their own digital circuits, forming them on a board as they place representative tiles onto it. They can then view in real time how their circuits are affected by certain inputs or restructuring of connections. This would be a useful supplement in the course that helps to emphasize the descriptive, and not procedural, nature of HDLs.